The A16 is a 16 bit RISC CPU with Harward load/store architecture.
- 8 registers, the program counter is mapped to register 8.
- Conditional execution of all instructions.
- Condition flags are set on demand.
- All instructions execute in a single clock cycle.
- Branch-link instruction where the program counter is copied to R6.
| Description syntax | |
| < > | Optional |
| (x|y) | Either x or y but not both |
| #exp | Constant Expression % - Binary & - Hexadecimal ¤ - Octal " - Ascii << - multiply by 2^n |
| Rd | Destination register (R0-R6, PC) |
| Ra | First operand Register |
| Rb | Second operand Register |
| Opcode | Operator code |
| cond | One of four conditions for execution EQ - Equal (Zero set) NE - Not Equal (Zero clear) CS - Carry Set CC - Carry Clear |
| s | Update condition code flags |
| Z | Condition code Zero flag |
| C | Condition code Carry flag |
| Arithmetic and logical opcode<cond|s> Rd, Rb, (Ra|#exp) #exp has a range of 0-15 (0-7 when <cond> is specified) Rd can't be PC when <s> is specified |
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| Opcode | Name | Operation | Flags Affected |
| ADD | Add | Rd = Rb + Ra | Z C |
| SUB | Subtract | Rd = Rb - Ra | Z C |
| AND | Bitwise AND | Rd = Rb AND Ra | Z |
| ORR | Bitwise OR Register | Rd = Rb OR Ra | Z |
| EOR | Bitwise Exclusive-OR | Rd = Rb EOR Ra | Z |
| Move opcode<cond> Rd, (Ra|#exp) #exp has a range of -256 to 255 (-64 to 63 when <cond> is specified) |
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| Opcode | Name | Operation | Flags Affected |
| MOV | Move | Rd = Ra | Z |
| MOV | Move | Rd = #exp | - |
| Comparison opcode Rd, (Ra|#exp) #exp has a range of 0-15 |
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| Opcode | Name | Operation | Flags Affected |
| CMN | Compare Negative | Rd + Ra | Z C |
| CMP | Compare | Rd - Ra | Z C |
| TST | Test | Rd AND Ra | Z |
| TOR | Test OR | Rd OR Ra | Z |
| TEQ | Test Equivalence | Rd EOR Ra | Z |
| Load/store opcode<cond|s> Rd, (Ra,#exp) #exp has a range of 0-15 (0-7 when <cond> is specified) |
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| Opcode | Name | Operation | Flags Affected |
| LDR | Load Register | Rd = [Ra] | Z |
| STR | Store Register | [Ra] = Rd | Z |
| Branching and program flow opcode<cond> label label has a range of 0-2047 (0-511 when <cond> is specified) |
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| Opcode | Name | Operation |
| B | Branch | PC = label |
| BL | Branch Link | R6 = PC, PC = label |
| RET | Return | PC = R6 + 1 |
| SKP | Skip next instruction | PC = PC + 2 |
| Shifting opcode<cond|s> Rd, Ra |
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| Opcode | Name | Operation | Flags Affected |
| LSL | Logical Shift Left | Rd = Ra << 1 | Z C |
| LSR | Logical Shift Right | Rd = Ra >> 1 | Z C |
| ROR | Rotate Right | Rd = Ra[0] -> (Ra >> 1) | Z C |
| SWP | Swap | Rd = (Ra << 8) OR (Ra >> 8) | Z |
| SWM | Swap Mask | Rd = (Ra >> 8) and 255 | Z |
| Assembler directives and misc | ||
| Opcode | Name | Operation |
| EQU #exp | Emit #exp at current assembly address counter | |
| ORG #exp | Set assembly address counter | |
| NOP | No-operation | For debugging and timing purposes |
| kcc | Meaning |
| "00x" | don't set cc | data2 = 0 |
| "01x" | set cc | data2 = 1 |
| "0x0" | data1 = 0 |
| "0x1" | data1 = 1 |
| "100" | ne - not equal (zero clear) |
| "101" | eq - equal (zero set) |
| "110" | cs - carry clear |
| "111" | cc - carry set |
| Meaning | |
| o | operator code |
| k | enable conditionals |
| c | conditional |
| i | immediate |
| a | operand 1 |
| b | operand 2 |
| d | destination |
| Instruction encoding | ||
| ooo | Normal instructions "ooo kcc i bbb aaa ddd" | |
| 0 | add<cc|s> rd,rb,(ra|#exp) | Rd = Rb + (Ra|(0|c)aaa)* |
| 1 | sub<cc|s> rd,rb,(ra|#exp) | Rd = Rb - (Ra|(0|c)aaa)* |
| 2 | and<cc|s> rd,rb,(ra|#exp) | Rd = Rb and (Ra|(0|c)aaa)* |
| 3 | orr<cc|s> rd,rb,(ra|#exp) | Rd = Rb or (Ra|(0|c)aaa)* |
| 4 | eor<cc|s> rd,rb,(ra|#exp) | Rd = Rb eor (Ra|(0|c)aaa)* |
| 5 | mov<cc> rd, #exp | Rd = iiiiiiii (ii|cc)bbbaaa |
| 6 | b<l><cc> label | PC = (00|cc)bbbaaaddd, if i then R6 = PC |
| 7 | Extended instructions "111 kcc i ooo aaa ddd" | |
| 0 | ldr<cc|s> rd,[(ra|#exp)] | Rd = [Ra|(0|c)aaa] |
| 1 | str<cc|s> rd,[(ra|#exp)] | [Ra|(0|c)aaa] = Rd |
| 2 | <lsr|ror><cc|s> rd,ra | Rd = (Rb[0] and i) -> (Rb >> 1) |
| 3 | <swp|swm><cc|s> rd,ra | Rd = Ra[0-7][8-15] and "iiiiiiii 11111111" |
| 4 | Reserved | |
| 5 | Reserved | |
| 6 | Reserved | |
| 7 | Reserved | |
| *if Rd=PC and kcc="01x" then Rd = Rd | ||
Sample code |
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| Multiplication | mul
mov r2,#0 domul lsrs r0,r0 addcs r2,r2,r1 add r1,r1,r1 bne domul ret |
| Division | |
| Square-root | |
| Bitcount | bitc mov
r1,#0 dobitc lsrs r0,r0 addcs r1,r1,#1 bne dobitc ret bitc2 mov r1,#0 dobtc2 sub r2,r0,#1 ands r0,r0,r2 add r1,r1,#1 bne dobtc2 ret |
| Pseudorandom number generator | rnd swp
r2,r0 sub r0,r1,r2 eor r1,r0,r1 ret |